Chameleon Chip

Chameleon Reconfigurable Processor

Chameleon processor

A chameleon chip is a reconfigurable microprocessor. It has an erasable hardware. It is also possible to rewire it by self. So the chameleon chip can be adapted to programming tasks. Reconfigurable processor consists of functional blocks which are connected paralleling. The functional blocks are computational blocks which consist of many computational units which can process simultaneously. While reconfiguring these chips, the connections are changed. i.e., the connections between blocks and also inside blocks are changed. After loading the software, hardware design at present will be erased and a new hardware design is generated by activating some connections and inactivating some connections. It defines the configuration of hardware for that software. Chameleon chip requires almost 20 microseconds for reconfiguration. Some of the reconfigurable processors are Chameleon chips, Billions of Operation (BOPS) and Parallel Array Computing Technology (PACT).

Multifunctional implementation

In conventional ASIC and FPGA, they require different hardware modules for multiple algorithms. For four algorithms, the chameleon chip is divided into 4 functional areas. While in the reconfigurable technology, only one reconfigurable fabric is required to load the entire four programs. Chameleon chips are able to rewire themselves to run the software. It is designed to solve communication systems. It is highly reconfigured. It can work on high bandwidth Reconfigured Communication Processor (RCP). This chameleon chip is faster, cheap and multitasking chips. 

First the algorithm 1 is loaded into the reconfigurable fabric. Algorithm 2 is loaded during algorithm 1 is processed. When the processing of algorithm 2 is done, then algorithm 3 is loaded. Thus the four algorithms are loaded into the reconfigurable fabric. The main thing is only one algorithm can be loaded at one time. The main advantages of chameleon chip are:-

• Lower cost
• Power consumption is low
• Low cost
• It can create customized communication signal processors.
• Increased performance

Architecture of Chameleon Chip

The design of machine contains pins used as configurable pins, data pins and control pins. The inside chip determines the set of function blocks (FB). It is used to construct the circuits, to interconnect the circuits and the input and output connections. Logic circuits are the main parts. According to the data in configuration memory, it will configure the function blocks. There are several connections between these functional blocks and these connections are encoded into bits. This configuration bits will be loaded into configuration memory. After these a machine will develop. The architecture of reconfigurable processor is shown below.

                                                                                     Chameleon Chip

Reconfigurable Processing Fabric (RPF)

It provides the unmatched algorithmic computation power to the chameleon chip. The fabric is divided into slices.

Programmable Input/Output

It consists of programmable Input output pins. It provides large bandwidth.

The technologies are:-

1. eCONFIGURABLE™ TECHNOLOGY :- It can be used for instantaneous reconfiguration. Using this technology the 4 algorithms can be loaded into the entire fabric. Only one algorithm can be loaded at one time.
2. C-SIDE Development tools:-  By using this technology, the user can program themselves. It helps to maintain the algorithm as secret.
3. eBIOS:- The embedded system is interfaced with reconfigurable fabric using this technology. It provides DMA services, configuration management etc.

The flowchart of design process is given below.

                                             Chameleon Chip design Process

Comparison of Chameleon Chip

Applications of Chameleon Chip

• Wireless Local Loop (WLL):- Due to the high processing power, large bandwidth of reconfigurable processor, the reconfigurable technology is used in WLL.
• Software defined radio: - This concept can be applied in cell phone technology.
• Wireless base stations: - The base station uses reconfigurable technology.
• High performance DSL: - Provide high bandwidth to users.